Position: DFT Engineer
Experience: 4-15 Yrs
Job Location : Bangalore
- SCAN stuck-at and at-speed techniques.
- Fundamentals of SCAN stuck-at and at-speed techniques.
- Expertise in handling Mentor Graphics EDT logic.
- Knowledge on On chip clock controller (OCC).
- Pattern generation with Mentor Graphics TestKompress Tool.
- Good knowledge in BSCAN operations. Knowleedge in MBIST Operations.
- Expertise in handling Synopsys SMS tool sets (Integrator, Builder, Yield Accelerator).
- Excellent track of pattern simulation and coverage analysis (preferred cadence ncsim simulator expert Experience in ATPG, Scan, BIST and Mentor TestKompress.
- Expert in writing test benches (Verilog, system Verilog) and tests for different components like PLL, ADC etc for generating ATE vectors.
- Experienced engineers with DFT flow, ATPG, Scan, BIST and Mentor TestKompress.
- Experience with the mentor tool sets.
- Familiarity with scan, membist, jtag concepts and 3rd party tools.
- Tester program creation, debug, and validation of DFT features on ATE.
Salary: Not Disclosed by Recruiter
Industry:Semiconductors / Electronics
Functional Area:Engineering Design, R&D
Role Category:Engineering Design
Role:Technical Lead/Project Lead
Employment Type:Permanent Job, Full Time
Desired Candidate Profile
Contact Company:Magna HR Consultants India Pvt Limited